library verilog;
use verilog.vl_types.all;
entity RPM_LUT is
    port(
        count           : in     vl_logic_vector(15 downto 0);
        dig1            : out    vl_logic_vector(3 downto 0);
        dig2            : out    vl_logic_vector(3 downto 0);
        dig3            : out    vl_logic_vector(3 downto 0)
    );
end RPM_LUT;
